VLSI DESIGN

Trusted by over 1 million members

Try Scribd FREE for 30 days to access over 125 million titles without ads or interruptions! Start Free Trial Cancel Anytime.

















































VLSI DESIGN Reference Material

By Verilog Course Team Where Technology and Creativity Meet



















































Contact Us VERILOG COURSE TEAM

Email:[email protected] Blog: www.vlsiprojects.blogspot.com Web: www.verilogcourseteam.com Phone: +91 98942 20795 Revision: 1

For hardcopies drop a mail or contact us.

Disclaimer: Due care and diligence has been taken while editing of this material. Verilog Course Team does not warrant or assume any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed. No warranty of any kind, implied, expressed or statutory, including to fitness for a particular purpose and freedom from computer virus, is given with respect to the contents of this material or its hyperlinks to other Internet resources. The material acts as just a reference to move forward and understand the concept. Reference in this material to any specific commercial products, processes, or services, or the use of any trade, firm or corporation name is for the information, and does not constitute



















































About Verilog Course Team

Verilog Course Team is a Electronic Design Services (EDS) for VLSI / EMBEDDED and MATLAB, delivering a wide variety of end-to-end services ,

including design , development, & testing for customers around the world .With proven expertise across multiple domains such as Consumer Electronics Market ,Infotainment, Office Automation, Mobility and Equipment Controls. Verilog Course Team is managed by Engineers / Professionals possessing significant industrial industrial experience across various application domains and engineering horizontals . Our engineers have expertise across a wide range of

technologies, to the efforts of

engineering our clients. Leveraging standards based components and investments in dedicated test lab

infrastructure; we offer innovative, flexible and cost-effective

Services and solutions.

Our Mission

Our mission is to provide cost effective, technology independent, good quality reusable Intellectual Property cores

with quality and cost factor are our

important constraints so as to satisfy our customers ultimately. We develop and continuously evaluate systems so as to pursue quality in all our deliverables. At our team, we are completely dedicated to customer’s requirements. Our products

are

designed and devoted to empower their competitive edge and help help them succeed. succeed.

Visit www.verilogcourseteam.com for more details.



















































Preface The India Semiconductor Association (ISA), an Indian semiconductor industry organization, has briefed growth, trends and forecasts for the Indian semiconductor market in collaboration with a U.S. consulting company Frost & Sullivan. The report titled as "ISA-Frost & Sullivan 2007/2008 Indian Semiconductor Market Update." According to the report, total semiconductor consumption in India (total value of semiconductors used for devices marketed in India) was $2.69 billion (USD) in 2006. The $2.69 billion represents 1.09% of the global semiconductor market. Of the total semiconductor consumption in India, consumption by local Indian set manufacturers accounted for $1.26 billion. The overall Indian semiconductor consumption will grow at an average rate of 26.7% per year in 2006 through 2009. Based on the actual consumption in 2006, the overall Indian semiconductor consumption is forecast to be $5.49 billion in 2009. This represents 1.62% of the global semiconductor market in 2009. Semiconductor consumption by local Indian set manufacturers is predicted to increase at 35.8% per year in 2006 through 2009 and amount to $3.18 billion in 2009. This material is the result of the Verilog Course Team’s practical experience both in Design/Verification and Training. Many of the examples illustrated throughout the material are real designs models. With Verilog Course Team’s training experience has led to step by step presentation, which addresses common mistakes and hard-to-understand concepts in a way that eases learning. Verilog Course Team invites suggestion and feedbacks from both students and faculty community to improve the quality, content and presentation of the material.



















































VLSI DESIGN UNIT-I CMOS TECHNOLOGY

1. An overview of silicon semiconductor technology

1

1.1 The Fabrication of a Semiconductor Device

1

1.1.2 Wafer Fabrication

2

1.1.3 Assembly

6

1.2 Basic CMOS Technology

8

1.2.1 A Basic n-well CMOS Process

9

1.2.2 A Basic p-well CMOS Process

13

1.2.3 Twin-Tub (Twin-Well) CMOS Process

13

1.2.4 Silicon On Insulator (SOI) Process

14

1.3 INTERCONNECT

18

1.3.1 Metal Interconnect

18

1.3.2 1.3.2 Po lys ili con /Refractory Metal Interconnect

19

1.3 .3 Local Interconnect

20

1.4 CIRCUIT ELEMENTS

21

1.4.1 Resistors

21

1.4.2 Capacitors

21

1.4.3 Electrically Alterable ROMs

23

1.4.4 Bipolar Transistors

24

1.4.5 LatchUp

26

1.4.5.1 The Physical Origin of Latchup

26

1.4.5.2 Latchup Triggering

28

1.4.6 Latchup Prevention

29

1.5. LAYOUT DESIGN RULES

30

1.5.1 Layer Representations

31

1.5.2 CMOS n-well Rules

32





















































VLSI DESIGN 1.5.4 SOI Rules

34

1.5.5 Layer Assignments

35

1.6 PHYSICAL DEISGN

35

1.6.1 Basic Concept

35

1.6.2 CAD Tools sets

37

1.6.3 Physical Design-The Inverter

38

1.6.4 Physical Design-The NOR

38

1.6.5 Physical Design-The NAND

39

1.7 DESIGN STRATEGIES

39

1.7.1 Structured Design Strategies

40

1.7.2 Hierarchy

40

UNIT 2 MOS TRANSISTOR THEORY

2 .1 NMOS ENHANCEMENT TRANSISTOR

41

2.2 PMOS ENHANCEMENT TRANSISTOR

45

2.3 THRESHOLD VOLTAGE

45

2. 3. 1 Threshold Threshold Voltage Equations Equations

46

2.4 BODY EFFECT

48

2.5 MOS Device Design Equations

48

2.5.1 Basic DC Equations

48



















































VLSI DESIGN 2.8THE COMPLEMENTARY CMOS INVERTER – DC CHARACTERISTICS

55

2.8.1 βn/β p ratio

61

2.8.2 Noise Margin

62

2.9 THE TRANSMISSION GATE

64

2.10 THE TRISTATE INVERTER

68

UNIT 3 SPECIFIFCATION OF VERILOG HDL

3. HISTORY OF VERILOG

69

3.1 BASIC CONCEPTS

69

3.1.1 Hardware Description Language

69

3.1.2 VERILOG Introduction

69

3.1.3 VERILOG Features

70

3.1.4 Design Flow

70

3.1.5 Design Hierarchies

73

3.1.5.1 Bottom up Design

73

3.1.5.2 Top-Down Design

74

3.1.6 Lexical Conventions

74

3.1.6.1 Whitespace

75

3.1.6.2 Comments

75



















































VLSI DESIGN 3.1.9.1 Data Types Value set

79

3.1.9.2 Nets

79

3.1.9.3 Vectors

80

3.1.9.4 Integer, Real and Time Register Data Types

80

3.1.9.5 Arrays

81

3.1.9.6 Memories

82

3.1.9.7 Parameters

82

3.1.9.8 Strings

82

3.2 MODULES

83

3.2.1 Instances

84

3.3 PORTS

84

3.3.1 Port Declaration

85

3.3.2 Port Connection Rules

85

3.3.3 Ports Connection to External Signals

86

3.4 GATE DELAYS

87

3.4.1 Rise, Fall, and Turn-off Delays

87

3.4.2 Min/Typ/Max Values

88

3.5 MODELING CONCEPTS

89

3.6 3.6 SW SWIT ITCH CH LE VE L MODELING

90

3.6.1 Switch level primitives

91



















































VLSI DESIGN 3.9 GATE LEVEL MODELING

101

3.9.1 Gate Types

101

3.10 BEHAVIORAL AND RTL MODELING

108

3.10.1 Operators

108

3.10.1.1 Arithmetic Operators

108

3.10.1.2 Relational Operators

109

3.10.1.3 Bit-wise Operators

110

3.10.1.4 Logical Operators

112

3.10.1.5 Reduction Operators

113

3.10.1.6 Shift Operators

114

3.10.1.7 Concatenation Operator

115

3.10.1.8 Replication Operator

116

3.10.1.9 Conditional Operator

116

3.10.1.10 Equality Operators

117

3.10.2 Operator Precedence

119

3.10.3 Timing controls

119

3.10.3.1 Delay-based timing control

119

3.10.3.2 Event based timing control

122

3.10.3.3 Level-Sensitive Timing Control

124

3.10.4 Procedural Blocks

124



















































VLSI DESIGN 3.10.12.1 The Conditional Statement if-else

131

3.10.12.2 The Case Statement

132

3.10.12.3 The casez and casex statement

134

3.10.13 Looping Statements

136

3.10.13.1 The forever statement

136

3.10.13.2 The repeat statement

136

3.10.13.3 The while loop statement

137

3.10.13.4 The for loop statement

138

3.11 DATA FLOW MODELING AND RTL

139

3.11.1 Continuous Assignment Statements

139

3.11.2 Propagation Delay

141

3.12 STRUCTURAL GATE LEVEL DESCRIPTION

141

3.12.1 2 to 4 Decoder

141

3.12.2 Comparator

142

3.12.3 Priority Encoder

144

3.12.4 D-latch

144

3.12.5 D Flip Flop

145

3.12.6 Half adder

145

3.12.7 Full adder

146

3.12.8 Ripple Carry Adder

146





















































VLSI DESIGN 4.3 TRANSMISSION GATES

153

4.3.1Multiplexers

153

4.3.2 Lathes

153

4.4 CMOS CHIP DESIGN OPTIONS

154

4.4.1 ASIC

154

4.4.2 Uses of ASICs

155

4.4.3 Full Custom ASICs

155

4.4.5 Semi-Custom ASICs

156

4.4.6 Standard- Cell-Based ASIC

156

4.4.7 Gate Array Asic

157

4.4.8 Channeled Gate Array

158

4.4.9 Channelless Gate Array

158

4.4.10 Structured Gate Array

159

4.5 PROGRAMMABLE LOGIC

159



















































VLSI DESIGN 5.2.1.2 Short-Circuit and Open-Circuit Faults

168

5.2.2 Observability

170

5.2.3 Controllability

171

5.2.4 Fault Coverage

171

5.2.5 Automatic Test Pattern Generation (Atpg)

171

5.2.6 Fault Grading And Fault Simulation

177

5.2.7 Delay Fault Testing

178

5.2.8 Statistical Fault Analysis

179

5.2.9 Fault Sampling

180

5.3 DESIGN STRATEGIES FOR TEST

180

5.3.1 Design for Testability

180

5.3.2 Ad-Hoc Testing

181

5.3.3 Scan-Based Test Techniques

184

5.3.3.1 Level Sensitive Scan Design (LSSD)

185



















































VLSI DESIGN 5.5.1.1 Introduction

196

5.5.1.2 The Test Access Port (TAP)

197

5.5.1.3 The Test Architecture

197

5.5.1.4 The TAP controller

198

5.5.1.5 The Instruction Register (IR)

198

5.5.1.6 Test-Data Registers

199

5.5.1.7 Boundary Scan Registers

199



















































VLSI DESIGN

CMOS TECHNOLOGY

UNIT-I An overview of silicon semiconductor technology Silicon in its pure or intrinsic state is a semiconductor, having a bulk electrical resistance somewhere between that of a conductor and an insulator. The conductivity of silicon can be varied over several orders of magnitude by introducing impurity atoms onto silicon crystal lattice. These dopants may either supply free electrons or holes. Impurity elements that use electrons are referred to as acceptors, since they accept some of the electrons already in the silicon, leaving vacancies or holes. Similarly, donor elements provide electrons. Silicon that contains a majority of donors is known as n-type and that which contains a majority are brought together, the region where the silicon changes from n-type and p-type materials are brought together, the region where the silicon changes from n-type to p-type is called a junction. By arranging junctions in certain physical structures and combining these with other physical structures, various semiconductor devices may be constructed. Over the years, silicon semiconductor processing has evolved sophisticated techniques for building these junctions and other structures having special properties. An integrated circuit is a small but sophisticated device implementing several electronic functions. It is made up of two major parts: a tiny and very fragile



















































VLSI DESIGN

CMOS TECHNOLOGY

Figure 1.1 Manufacturing Flow Chart of an Integrated Circuit 1.1.2 Wafer Fabrication (Front-End)

Identical integrated circuits, called die, are made on each wafer in a multi-step process. Each step adds a new layer to the wafer or modifies the existing one. These layers form the elements of the individual electronic circuits. The main steps for the fabrication of a die are summarized in the following table. Some of them are repeated several times at different stages of the process. The order given here doesn't reflect the real order of fabrication process.





















































VLSI DESIGN

CMOS TECHNOLOGY

Ionic Implantation

It allows to introduce a dopant at a given depth into the material using a high energy electron beam.

Metal Deposition

It allows the realization of electrical connections between the different cells of the integrated circuit and the outside. Two different methods are used to deposit the metal: evaporation or sputtering.



















































VLSI DESIGN

CMOS TECHNOLOGY

parameters during the process. Ionic implantation process is simpler than diffusion process but more costly (ionic implanters are very expensive machines).



















































VLSI DESIGN

CMOS TECHNOLOGY

Figure 1.4 Metal Deposition Process



















































VLSI DESIGN

CMOS TECHNOLOGY

one particle whose diameter is superior to 0.5 micron (and doesn’t exceed 1 micron) inside one cubic foot of air . All these processes are part of the manufacturing phase of the chip itself. Silicon chips are grouped on a silicon wafer (in the same way postage stamps are printed on a single sheet of paper) before being separated from each other at the beginning of the assembly phase. Wafer Probing. This step takes place between wafer fabrication and assembly. It verifies the functionality of the device performing thousands of electrical tests, by means of special microprobes. Wafer probing is composed of two different tests: 1. Process parametric test : This test is performed on some test samples and



















































VLSI DESIGN

CMOS TECHNOLOGY

The first step of assembly is to separate the silicon chips: this step is called die cutting (figure 1.7). Then, the dies are placed on a lead frame: the “leads” are the chip legs (which will be soldered or placed in a socket on a printed circuit board. On a surface smaller than a baby's fingernail we now have thousands (or millions) of electronic components, all of them interconnected and capable of implementing a subset of a complex electronic function. At this stage the device is completely functional, but it would be impossible to use it without some sort of supporting system. Any scratch would alter its behavior (or impact its reliability), any shock would cause failure. Therefore, the die must be put into a ceramic or plastic package to be protected from the external world.





















































VLSI DESIGN

CMOS TECHNOLOGY



















































VLSI DESIGN

CMOS TECHNOLOGY

CMOS is also sometimes referred to as complementary-symmetry metal–



















































VLSI DESIGN

CMOS TECHNOLOGY

Once the n-well is created, the active areas of the nMOS and pMOS transistors



















































VLSI DESIGN

CMOS TECHNOLOGY



















































VLSI DESIGN

CMOS TECHNOLOGY

Metal (aluminum) is deposited over the entire chip surface using metal



































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































































VLSI DESIGN

MOS TRANSISTOR THEORY

Under normal conditions that is, when V gs >V t the depletion-layer width remains constant and charge carriers are pulled into the channel from the source. However, as the substrate bias V sb (V source-V substrate ) is increased, the width of the channel substrate depletion layer also increases, resulting in an increase in the density of the trapped carriers in the depletion laver. For charge neutrality to hold, the channel charge must decrease. The resultant effect is that the substrate voltage, V sb , adds to the channelsubstrate junction potential. This increases the gate-channel voltage drop. The overall effect is an increase in the threshold voltage V t (V t2 -V t1 )

Figure 2.5 The effect of substrate bias on series-connected n-transistors

2.5 MOS DEVICE DESIGN EQUATIONS 2.5.1 Basic DC Equations

The MOS transistors have three regions of operation: • • •

Cutoff or subthreshold region. Nonsaturation or linear region. Saturation region.

The ideal (first order, Shockley) equations describing the behavior of an nMOS device in the three regions are:

The cutoff region: Ids=0

Vgs≤ Vt

The nonsaturation, linear or triode region:

(2.5a)



















































VLSI DESIGN

MOS TRANSISTOR THEORY 2

Ids=(β =(β/2)(Vgs-Vt)

(2.5c)

where Ids is the drain-to-source current, V gs is the gate-to-source voltage, V t is the device threshold, and β is the MOS transistor gain factor. The last factor is dependent on both the process parameters and the device geometry, and is given by β=(µє =(µє/tox)(W/L)

(2.6)

where µ is the effective surface mobility of the carriers in the channel, є is the permittivity of the gate insulator, t ox is the thickness of the gate insulator, W is the width of the channel, and L is the length of the channel. The gain factor β thus consists of a process dependent factor µ є/tox , which contains all the process terms that account for such factors as doping density and gate-oxide thickness and a geometry dependent term (W/L), which depends on the actual layout dimensions of the device. The process dependent factor is sometimes written as µC ox, where C ox = є / t o x is the gate oxide capacitance. The geometric terms in Eq. (2.6) are illustrated in figure 2.6 in relation to the physical MOS structure.

Figure 2.6 Geometric terms in the MOS device equation

Figure 2.7 VI characteristics for n- and p-transistors



















































VLSI DESIGN


The voltage-current characteristics of the n- and p-transistors in the non-saturated and saturated regions are represented in figure 2.7 (with the SPICE circuit for obtaining these characteristics for an n-transistor). Note that we use the absolute value of the voltages concerned to plot the characteristics of the p- and ntransistors on the same axes. The boundary between the linear and saturation regions corresponds corresponds to the condition | V ds ds| = | Vgs - V t | and appears as a dashed line in figure 2.7. The drain voltage at which the device becomes saturated is called Vdsat, or the drain saturation voltage. In the above equations that is equal to V gs-Vt 2.5.2 Second Order Effects

Equation 2.5 represents the simplest view of the MOS transistor DC voltage current equations. There have been many research papers published on more detailed and accurate models that have been created to fill a variety of requirements, such as accuracy, computational efficiency, and the conservation of charge. The circuit simulation program SPICE and its commercial and proprietary derivations generally use a parameter called LEVEL to specify which model equation, are LEVEL1 models build on those defined in Eq. (2.5) and include some important second order effects. LEVEL 2 models calculate the currents based on physics. LEVEL 3 is a semiempirical approach that relies on parameters selected on the basis of matching the equations to real circuits. The MOS device equations in terms of the LEVEL 1 parameters used in SPICE will be covered here. First the term µє µє/tox(µC ox ) is defined as the process gain factor. In SPICE this is referred to as KP. Depending on the vintage of the process and the type of transistor, KP may vary from 10-100 pA/V 2. In addition, it is not unusual to expect a variation of 10%-20% in KP within a given process as a result of variations in starting materials and variation in SiO 2 growth. 2.5.2.1 Threshold Voltage-Body Effect

The threshold voltage V t is not constant with respect to the voltage difference between the substrate and the source of the MOS transistor. This is known as the substrate-bias effect or body effect. The expression for the threshold voltage may be modified to incorporate V sb, the difference between the source and the substrate.

(2.7)



















































VLSI DESIGN


where Vsb is the substrate bias, V to is the threshold voltage for V sb=0 , and γ is the constant that describes the substrate bias effect. The term Ø b is defined in Eq 2.2. Typical values for γ for γ lie in the range of 0.4 to 1.2. It may be expressed as

(2.8) in which q is the charge on an electron, єox, is the dielectric constant of the silicon dioxide, єsi; is the dielectric constant of the silicon substrate, and N A is the doping concentration density of the substrate. The term γ is the SPICE parameter called GAMMA. Vto is the parameter VTO , N A is he parameter NSUB, and øs=2ø b is PHI, the surface potential at the onset of strong inversion. Thus the threshold shifts by approximately half a volt with the source at 2.5 volts for these process parameters. The type of CMOS process can have a large impact on this parameter for both n- and p-transistors. The increase in threshold voltage leads to lower device currents, which in turn leads to slower circuits. slower circuits. 2.5.2.2 Subthreshold Region

The cutoff region described by Eq. (2.5a) is also referred to as the subthreshold region where I ds increases exponentially with V ds and Vgs. Although the value value of Ids is very small ( I ds =0), the finite value of Ids may be used to advantage to construct very low power circuits or it may adversely affect circuits such as dynamic-charge storage nodes. As an approximation, Level 1 SPICE models set the subthreshold current to 0. 2.5.2.3 Channel-length Modulation

The simplified equations that describe the behavior of an MOS device assume that the carrier mobility is constant, and do not take into account the variations in channel length due to the changes in drain-to-source voltage, V ds . For long channel lengths, the influence of channel variation is of little consequence. However, as devices are scaled down, this variation should be taken into account. When an MOS device is in saturation, the effective channel length actually is decreased such that Leff =L-Lshort

(2.9)

where

The reduction in channel length increases the (W/L) ratio, thereby increasing β



















































VLSI DESIGN


source with infinite output impedance, the MOS device has a unite output impedance. An approximation that takes this behavior into account is represented by the following equation:

(2.10)

Where k is the process gain factor µ µєє/tox and λ is an empirical channel-length -1 -1 modulation factor having a value in the range 0.02V to 0.005V 2.5.2.4 Mobility Variation

The mobility µ, describes the ease with which carriers drift in the substrate material. It is defined by µ=average carrier drift velocity (V)/ Electric Field (E)

(2.11)

If the velocity, V, is given in cm/sec, and the electric field, E, in V/cm, the 2 mobility has the dimensions cm /V-sec. The mobility may vary in a number of ways. Primarily, mobility varies according to the type of charge carrier. Electrons (negative-charge carriers) in silicon have a much higher mobility than holes (positive-charge carriers), resulting in n-devices having higher current producing producing capability than the corresponding p-devices. Mobility decreases with increasing doping-concentration and increasing temperature. The temperature variation becomes less pronounced as the doping density increases. In SPICE is specified by the parameter U O .

2.6 MOS MODELS In the previous section the ideal equations that describe the behavior of MOS transistors. While these incorporate some non ideal effects (channellength modulation, threshold-voltage variation), they may not accurately model a specific device in a particular process. That is especially true for devices that have very small dimensions (gate lengths, gate widths, oxide thicknesses) as the modeling process becomes increasingly 3D in nature. Parameter

nMOS

pMOS

Units

Description Description

VTO

0.7

0.7

Volt

Threshold voltage

KP

8x10

GAMMA

0.4

-5

2.5x10 5

0.5

-

A/V

V0.5

2

Transconductance coefficient Bulk threshold parameter





















































VLSI DESIGN


PHI

0.37

0.36

volt

LAMBDA

0.01

0.01

Volt

LD

0.1 x -6 10

0.1x10

TOX

2x10

NSUB

6

-

Surface potential at strong inversion -1

Channel length modulation parameter

Meter

Lateral diffusion

Oxide thickness

-8

2x10

-8

Meter

16

2x10 4x10

16

1/cm

3

Substrate doping density

Table 2.1 SPICE DC Parameters Researchers have developed and refined a wide range of MOS models in an effort to predict more accurately the performance of MOS devices before they are fabricated for varying design scenarios. For instance, one might predict DC currents very accurately from raw process parameters, thus helping predict the behavior of an as yet untested device. However, because of the complexity of the model, it might not be appropriate for a fast execution time model that might be needed needed for digital simulatio simulation n purposes. purposes. In that case, a model based on parameters measured from an actual process might be appropriate. Depending on the particular circuit level simulator that may be available, a wide variety of MOS simulation models may be used. For instance in one commercial circuit simulators there are over 10 different MOS models. Many semiconductor vendors expend a great deal of effort to model the device they manufacture. Many times these efforts are aimed at internal



















































VLSI DESIGN


2.7 SMALL SIGNAL AC CHARACTERISTICS The MOS transistor can be represented by the simplified (V sb = 0) small signal equivalent model shown in figure 2.8 when when biased appropriately. Here the MOS transistor is modeled as a voltage-controlled current source (g m ), an output conductance (g ds ), and the interelectrode capacitances. These values may be used, for instance, to calculate voltage amplification factors (gain) or bandwidth characteristics when considered along with other circuit elements.

Figure 2.8 Small signal model for an MOS transistor The output conductance (g ds ds ) in the linear region can be obtained by differentiating Eq. (2.5b) with respect to V ds ds , which results in an output drainsource conductance of

gds = β ((V (( V gs - V t )-2 V ds ) ≈β(V ≈β(Vgs-Vt)

(2.12)

Note that consistent with Eq. (2.5b), V ds ds must be small compared to V gs for the MOS device to be in a linear operating regime. On rearrangement, the channel resistance R c is approximated by R c(linear) c(linear) =1/ β(Vgs-Vt)

(2.13)

which indicates that it is controlled by the gate-to-source voltage. The



















































VLSI DESIGN


In practice, however, due to channel shortening (Eq. 2.9) and other effects, the drain-current characteristics have some slope. This slope defines the g ds ds of the transistor. The output conductance can be decreased by lengthening the channel (i.e., L). The transconductance g m expresses the relationship between output current I ds and the input voltage V gs and is defined by (2.15)

It is used to measure the gain of an MOS device. In the linear region g given by (2.16) g m(linear) = β V ds and in the saturation region by g m(sat) = β(Vgs-Vt)

m

(2.17)

Since transconductance must have a positive value, the absolute value is used for voltages applied to p-type devices.

2.8 THE COMPLEMENTARY CMOS INVERTER – DC CHARACTERISTICS A complementary CMOS inverter is realized by the series connection of a p and an n-device, as shown in figure 2.11. In order to derive the DCtransfer characteristics for the inverter (output voltage, V ou ou , t as a function of the inverter V in ), from the Table 2.1, which outlines various regions of operation for the n- and p-transistors. In this table, V tn is the threshold tn voltage of the n channel device, and V tp tp , is the threshold voltage of the pchannel device. The objective is to find the variation in output voltage (V ou t ) for changes in the input voltage (V in ).



















































VLSI DESIGN


The graphical representation of the simple algebraic equations described by Eq. (2.5) for the two inverter transistors shown in figure 2.12(a). The absolute value of the p-transistor drain current I ds inverts this ds characteristic. This allows the VI characteristics for the p-device to he reflected about the x-axis (figure. 2.12b). This step is followed by taking the absolute value of the p-device, V ds ds , and superimposing the two characteristics characteristics yielding the resultant curves shown in Fig. 2.12(c).

Table 2.2 Relations Between Voltages for the Three Regions Of Operation Of A CMOS Inverter The input/output transfer curve may now be determined by the points of common V gs intersection in figure 2.10(c). Thus, solving for V in n = V i n p and I ds n =I ds p gives the desired transfer characteristics of a CMOS inverter as illustrated in figure 2.13. The switching point is typically designed to be 50 percent of the magnitude of the supply voltage: = V DD /2. During transition, both transistors in the CMOS inverter are momentarily "ON," resulting in a short pulse of current drawn from the power supply. This is shown by the dotted line in figure 2.11

The operation of the CMOS inverter can be divided into five regions (figure 2.13). The behavior of n- and p-devices in each of the regions may



















































VLSI DESIGN


Figure 2.10 Graphical derivation of CMOS inverter characteristic Region B. This region is characterized by V tn tn < Vin < V DD /2 in which the p-device is in its nonsaturated region (V ds ds ≠ 0) while the n-device is in saturation. The equivalent circuit for the inverter in this region can be represented by a resistor for the p-transistor and a current source for the n-transistor as shown in figure 2.12(a).

The saturation current I ds n for the n-device is obtained by setting V gs =V in . This result in Where βn=(µnε/tox)(Wn/Ln)





















































VLSI DESIGN

MOS TRANSISTOR THEORY 2

Idsp=-β =-β p (Vin-VDD-Vtp)(Vout-VDD)- (Vout-VDD) /2

(2.19)

Where β p=(µ pε/tox)(W p/L p) and an d Vtp=threshold voltage of p-device µ p =mobility of electrons W p=channel width of p-device L p=channel length of p-device Substituting I ds p =-I =- I ds n The output voltage V ou t can be expressed as (2.20)



















































VLSI DESIGN


Region C . In this region both the n and p device are in saturation. This is represented by schematic in figure 2.12(b) which shows two current sources in series. The saturation currents for the two devices are given by

I ds p =-( =- ( β p /2)(V in -V DD -V tp ) 2 I ds n =-( =- ( β n /2)(V in -V tn ) I ds p = -I ds n

With

2

This yields

(2.21)

By setting β n=β n= β p and V tn =-V =- V tp We obtain V in =V DD /2 (2.22) Which implies that region C exists only for one value of V in . The possible values of V ou t in this region can be deduced as follows n-channel:

V



















































VLSI DESIGN


Region D . This region is described by V DD /2 < V in ≤ V DD +V tp . The pdevice is in saturation while the n-device is operating in its nonsaturated region. This condition is represented by equivalent circuit shown in figure. The two currents may be written as

I ds p = (- β p /2)(V in -V DD -V tp ) and an d

2

2

I ds n = β n (V in -V tn )V ou t -(V -( V ou t /2) /2 ) with I ds p =-I =- I ds n The output voltage becomes (2.24)

Region E. This region is defined by input condition V in ≥ V DD -V tp , in which the p-device is cut off (I ds p =0), and the n-device is in the linear mode. Here , V gs p =V in -V DD , which is more positive than V tp .

Regi

Condition

p-device

n-device

Output



















































VLSI DESIGN The output in this region is Vout=0

MOS TRANSISTOR THEORY (2.25)

From the transfer curve of figure 2.13 it may be seen that the transition between the two states is very steep. This characteristic is very desirable because the noise immunity is maximized. For convenience, the characteristics associated with the five regions are summarized in Table 2.3. 2.8.1 βn/βp ratio

In order to explore the variations of the transfer characteristics as a function of βn/β p, the transfer curve for several values of βn/β p are plotted in figure 2.15. The gate-threshold voltage V inv where Vin=Vout is dependent on βn/β p . Thus for a given process, if we want to change βn/β p we need to change the channel dimensions, i.e., channel-length L and channel-width W. from from figure it can can be seen that as the ratio βn/β p is decreased the transition region shifts from left to right ; however, however, the output output voltage transition transition remains sharp. sharp. For the CMOS inverter a ratio of (2.26) βn/β p=1 may be desirable since it allows a capacitive load to charge and discharge in equal times by providing equal current-source and sink capabilities. F or inverter transfer curve is also plotted for W n/W p .This shows a relative shift to the left compared with β ratioed case because the p-device has inherently lower gain.



















































VLSI DESIGN

MOS TRANSISTOR THEORY -1.5

Ids α T

(2.28)

Since the voltage characteristics depend on the ratio βn/β p, and the mobility of both holes and electrons are similarly affected, this ratio is independent of temperature to a good approximation. Both V tn and Vtp decrease slightly as temperature increases, and the extent of region A is reduced while the extent of region E increases. Thus the overall transfer characteristics of figure shift to the 0 left as temperature increases. If the temperature rises by 50 C, the threshold drop by 200mV each. This would cause a 0.2V shift in the input threshold of the inverter. 2.8.2 Noise Margin

Noise margin is a parameter closely related to the input-output voltage characteristics. This parameter allows us to determine the allowable noise voltage on the input of a gate so that the output will not be affected. The specification most commonly used to specify noise margin is in terms of two parameters – the LOW noise margin, NM L and the HIGH noise margin NM H . NM L is defined as the difference in magnitude between the maximum LOW output voltage of the driving gate and the maximum input LOW voltage recognized by the driven gate. Thus NM L =| V ILmax - V OLmin |

(2.29)





















































VLSI DESIGN


Generally it is desirable to have V IH =VIL and for this to be a value that is midway in the “logic swing”, VOL to VOH . This implies that the transfer characteristics should switch abruptly, that is, there should be high gain in the transition region. For the purpose of calculating noise margins, the transfer characteristic of a typical inverter and the definition of voltage levels V IL, VOL, VIH , VOH are shown in figure 2.15. To determine V IL note that the inverter is in region B of operation, where the p-device is in its linear region while the n-device is in saturation. The VIL is found by using the unity gain point at the V OL end of the characteristic. For the inverter shown the NM L is 2.3 volts while the NM H is 1.7 volts. Note that if either NML or NMH for a gate are reduced, then the gate may be susceptible to switching noise that may be present on the inputs. Apart from



















































VLSI DESIGN


Figure 2.16 Transistor connection for CMOS transmission gate nMOS Pass Transistor:

Referring to figure2.17 (a), the load capacitor C load is initially discharged (i.e., V ou ou t = VSS ). With S = 0 (Vss) (i.e., Vgs= 0 volts), I ds ds = 0, then V out = VSS irrespective of the state of the input V in When S = 1 (V ), and V = 1, the pass



















































VLSI DESIGN


The overall behavior can be expressed as:

S=0(-S=1);

n-device =off p-device =off Vin=VSS, Vout=Z Vin=VDD, Vout=Z

Where Z refers to a high impedance state and



















































VLSI DESIGN


transistors are monitored. In reality, the capacitor charge would be exponential, but a linear ramp serves to show what happens to the pass transistor currents. As V ou t rises, the p-transistor current follows a constant V gs of -5 volts. That is, it starts out in saturation and transitions to the nonsaturated case when |V gs p -V tp |<|V ds p |. The n-transistor is always in the saturated region as V dsn =V gs n and V gsn -V tn < V dsn . When V ou t reaches a V tn delow V DD , the n-transistor turns off. Thus there are three regions of operation:



















































VLSI DESIGN


The total current decreases in magnitude as V in increases until V in=|Wtp(bodyaffected)|. Here the p-transistor turns on and in this case slows the decrease of current. When V in>VDD-Vtn(body-affected), the current starts to increase in magnitude as the p current continues to increase while the n transistor is off. In this simulation the p and n gains were matched. For the region |V tp|




















































VLSI DESIGN 2.10 THE TRISTATE INVERTER




















































VLSI DESIGN

UNIT 3

SPECIFICATION USING VERILOG HDL





























VLSI DESIGN

Recommend Documents