VLSI system design ECE 301 Electronic voting machine FPGA Implementation Implementation
Submitted by: Shyamsundar R 10BEC0445 Tushaar Vishnu 10BEC0169 Faculty: Slot:
Prof. Ravi S B1
Description This module can be used as a voting machine to count the number of votes for 4 separate candidates. It has a lock feature to prevent a voter from voting more than once. For the next voter the system has to be manually unlocked. The No of votes for each candidate and the total no of votes will be displayed. It was implemented in FPGA using Altera Cyclone II DE1, Quartus II was used to program the board. This module uses counters as the basic elements. When a vote is cast the corresponding counter is incremented by one, and the total count is also incremented. Clock, reset, unlock, and votes for the 4 candidates were given to the onboard slide switches, clock was given manually. The number of votes casted for each candidate as well as the total number of votes were displayed on LEDs. The locking mechanism we implemented is an innovative design. For a voter to vote the total number of unlocks should be greater than the total number of votes casted. Even if it is unlocked a number of times it will be counted as only one unlock unless a vote is cast in between. This module has many real time applications, however due to limitations of the board, we were able to achieve only limited functionality.
VERILOG CODE module counter1(rst,out,clk,a); input rst,clk,a; output reg [3:0] out; always@(posedge clk or posedge rst) begin if (rst) out=0; else if (a==1) out=out+1; end endmodule module counter2(rst,out,clk,a); input rst,clk,a; output reg [7:0] out; always@(posedge clk or posedge rst) begin if (rst) out=0; else if (a==1) out=out+1; end endmodule module evm(clk,a,b,c,d,reset,lock,ca,cb,cc,cd,totvot); input clk,a,b,c,d,reset,lock; output [3:0] ca,cb,cc,cd; output [7:0] totvot; wire k; wire [7:0] lc; assign k=(lc>ca+cb+cc+cd)?1:0; assign totvot=ca+cb+cc+cd; counter1 counta(reset,ca,clk,a&k); counter1 countb(reset,cb,clk,b&k); counter1 countc(reset,cc,clk,c&k); counter1 countd(reset,cd,clk,d&k); counter2 lockcount(reset,lc,lock,(lc==ca+cb+cc+cd)); endmodule
TEST BENCH module test_evm; reg a,b,c,d,reset,lock,clk; wire [3:0] ca,cb,cc,cd; wire [7:0] tot; evm m1(clk,a,b,c,d,reset,lock,ca,cb,cc,cd,tot); initial begin $monitor("ca=%d cb=%d cc=%d cd=%d tot=%d",ca,cb,cc,cd,tot); reset=0; clk=0; a=0; b=0; c=0; d=0; #21 reset=1; #21 reset=0; #21 lock=1; #21 lock=0; #21 a=1; #21 a=0; #21 b=1; #21 b=0; #21 lock=1; #21 lock=0; #21 c=1; #21 c=0; #1 lock=1; #3 lock=0; #5 b=1; #5 b=0; #21 lock=1; #21 lock=0; #21 a=1; #21 a=0; end always #1 clk=~clk; endmodule MONITORED OUTPUT # ca= x cb= x cc= x cd= x tot= x # ca= 0 cb= 0 cc= 0 cd= 0 tot= 0 # ca= 1 cb= 0 cc= 0 cd= 0 tot= 1 # ca= 1 cb= 0 cc= 1 cd= 0 tot= 2 # ca= 1 cb= 1 cc= 1 cd= 0 tot= 3 # ca= 2 cb= 1 cc= 1 cd= 0 tot= 4
